With the spectacular rise of personal computer and telecommunications technology, there has been an equally phenomenal development in the technology of ICs. In particular, with the drive to ever higher levels of circuit integration, the importance of conserving the real estate on a die and minimizing the consumption of power continues to draw the attention of scientists and engineers engaged in the design of ICs.
This is particularly true in the field of capacitance-sensing devices where there is a premium attached to producing devices with small size and minimal power consumption. The elimination of circuit designs which are overdesigned and suffer from inelegant use of the die real estate for integrated circuits used to drive capacitance-sensing devices is an area drawing the continued attention of scientists and engineers engaged in the development of capacitance-sensing devices. Thus, elegant circuit designs that reduce the number of circuit components on a die of an IC and minimize power consumption are of particular interest for maintaining a competitive edge in the field of capacitance-sensing devices and integrated-circuit technology, more generally.